1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, it relates to a structure of a DRAM (dynamic random access memory) which can input/output memory information at random, and a method of manufacturing the same.
2. Description of the Background Art
In general, a DRAM (dynamic random access memory) is known as a semiconductor memory device which can input/output memory information at random. Such a DRAM is generally provided with a memory cell array part which is a storage region for storing a number of data and a peripheral circuit part which is required for inputting/outputting data from/to the exterior.
FIG. 29 is a block diagram showing an exemplary structure of a general DRAM 150. Referring to FIG. 29, DRAM 150 comprises a memory cell array 151 for storing memory information, a row and column address buffer 152 for receiving address signals, for selecting memory cells forming unit memory circuits, from the exterior, a row decoder 153 and a column decoder 154 for specifying the memory cells by decoding the address signals, a sense refresh amplifier 155 for amplifying and reading data stored in the specified memory cells, a data-in buffer 156 and a data-out buffer 157 for inputting/outputting data, and a clock generator 158 for generating clock signals.
The memory cell array 151 occupying a large area on a semiconductor chip is provided with a plurality of memory cells for storing information, which are arranged in the form of a matrix. In general, each memory cell is formed by a single MOS transistor and a single capacitor which is connected thereto. Such a memory cell is widely known as a one-transistor one-capacitor memory cell. It is possible to readily improve the degree of integration of a memory cell array with such memory cells having simple structures, which are widely applied to a mass storage DRAM.
Further, such memory cells of the DRAM can be classified into some types in response to the structures of capacitors thereof. In a stacked type capacitor, for example, a principal part of the capacitor extends toward upper portions of a gate electrode and a field oxide film, so that opposite areas of electrodes are increased in the capacitor.
Consequently, it is possible to increase the capacitance of the capacitor. In the stacked type capacitor having such characteristics, it is possible to ensure its capacitance also when elements are miniaturized following high integration of a semiconductor device. Thus, the stacked type capacitor is widely employed following integration of the semiconductor device.
In a 256 megabit DRAM having further miniaturized elements, for example, it is difficult to ensure a constant capacitance even if stacked type capacitors are employed.
In order to increase the capacitance, therefore, there has been made an attempt of preparing a dielectric film of a capacitor from a high dielectric material (a material having a high dielectric constant) such as PZT (lead zirconate titanate ceramic) or the like. FIG. 30 shows an exemplary DRAM employing a high dielectric film of PZT or the like for a capacitor.
Referring to FIG. 30, field oxide films 103 are formed at a space on a p-type semiconductor substrate 101 gin element isolating regions of its main surface. Channel stopper layers 107 are formed under lower surfaces of the field oxide films 103.
Transfer gate transistors 102a and 102b are formed on element forming regions of the main surface of the semiconductor substrate 101. The transfer gate transistor 102a has impurity regions 105a and 105b for serving as source/drain regions, and a gate electrode 111b. On the other hand, transfer gate transistor 102b has impurity regions 105b and 105c for serving as source/drain regions, and a gate electrode 111c.
The gate electrodes 111b and 111c are formed on the main surface of the semiconductor substrate 101 with gate insulating films 109 interposed therebetween. On the other hand, gate electrodes 111a and 111d are also formed on the field oxide films 103 respectively.
Oxide films 113 are formed to cover the gate electrodes 111a, 111b, 111c and 111d. A buried bit line 116 is formed to extend from a surface of the impurity region 105b toward surfaces of the oxide films 113. A flattened first interlayer insulating film 115 is formed to cover the buried bit line 116 and the oxide films 113.
First interlayer insulating film 115 is provided with contact holes 117 reaching impurity regions 105a and 105c. Plugs 118 of polycrystalline silicon or the like are formed in contact holes 117. Capacitors 120 are formed on first interlayer insulating film 115. Capacitors 120 have lower electrodes 121 of platinum (Pt) or the like, high dielectric films 123, and upper electrodes 125 of platinum (Pt) or the like.
Barrier layers 119 of TiN or the like are formed along upper surfaces of plugs 118 and first interlayer insulating film 115. Lower electrodes 121 of capacitors 120 are formed on barrier layers 119. Due to such provision of the barrier layers 119, it is possible to inhibit the materials forming lower electrodes 121 of capacitors 120 and plugs 118 from mutual diffusion.
A second interlayer insulating film 127 is formed to cover the capacitors 120. In second interlayer insulating film 127, contact holes 129 are formed in portions located on the upper electrodes 125 of capacitors 120. An interconnection layer 131 of aluminum (Al) or the like is formed on inner surfaces of contact holes 129 and on second interlayer insulating film 127.
Positional relation between capacitors 120 and plugs 118 in the conventional DRAM shown in FIG. 30 is now described with reference to FIG. 31. FIG. 31 is a plan view typically showing the positional relation between capacitors 120 and plugs 118. Throughout the specification, the term "capacitor" (120) indicates a portion having a stacked structure of a lower electrode (121), a high dielectric film (123) and an upper electrode (125), to substantially function as a capacitor. A section taken along the line XXX--XXX in FIG. 31 corresponds to that shown in FIG. 30.
Referring to FIG. 31, plugs 118 and capacitors 120 overlap with each other in a plan view.
With reference to FIGS. 32 to 41, steps of manufacturing the conventional DRAM shown in FIG. 30 are now described. FIGS. 32 to 41 are partial sectional views showing first to tenth steps of manufacturing the conventional DRAM.
Referring to FIG. 32, field oxide films 103 are formed in element isolating regions of the main surface of p-type semiconductor substrate 101 by selective oxidation or the like. At this time, a p-type impurity is previously introduced into the element isolating regions in formation of the field oxide films 103, thereby forming channel stopper layers 107 simultaneously with field oxide films 103.
Then, gate insulating films 109 are formed on the main surface of semiconductor substrate 101 by thermal oxidation or the like. Gate electrodes 111a, 111b, 111c and 111d are formed on gate insulating films 109. These gate electrodes 111a, 111b, 111c and 111d are employed as masks to introduce an n-type impurities into the main surface of semiconductor substrate 101, thereby forming impurity regions 105a, 105b and 105c. Then, oxide films 113 are formed to cover gate electrodes 111a, 111b, 111c and 111d.
Referring to FIG. 33, a conductive layer 116a of polycrystalline silicon or the like is formed by CVD or the like. Referring to FIG. 34, conductive layer 116a is patterned to form a buried bit line 116 on impurity region 105b. Then, a first interlayer insulating film 115 is formed to cover buried bit line 116 and oxide films 113 by CVD or the like. Then, first interlayer insulating film 115 is flattened by heat treatment.
Referring to FIG. 35, contact holes 117 are formed in regions of first interlayer insulating film 115 located on impurity regions 105a and 105c. Referring to FIG. 36, a conductive layer 118a of polycrystalline silicon or the like is formed on inner surfaces of contact holes 117 and on first interlayer insulating film 115.
Referring to FIG. 37, conductive layer 118a is etched back by dry etching, thereby forming plugs 118. At this time, the upper surface of first interlayer insulating film 115 is overetched not to leave conductive layer 118a in step portions (not shown). Thus, upper surfaces of plugs 118 are lower in contact holes 117.
Referring to FIG. 38, a barrier layer 119 of TiN, Ta, Ti/TiN/Ti or the like is deposited by sputtering or the like on plugs 118 and first interlayer insulating film 115. A lower electrode 121 of platinum (Pt) or the like is formed on barrier layer 119 by sputtering or the like. Further, a high dielectric film 123 of SrTiO.sub.3 or the like is formed on lower electrode 121 at a temperature of not more than about 550.degree. C. by sputtering or the like. An upper electrode 125 of platinum (Pt) or the like is formed on high dielectric film 123 again by sputtering or the like.
Referring to FIG. 39, resist patterns 140 which are patterned in the form of capacitors are formed on upper electrode 125. The resist patterns 140 are employed as masks to carry out etching, thereby forming capacitors 120, as shown in FIG. 39.
Referring to FIG. 40, a second interlayer insulating film 127 is formed to cover capacitors 120 by CVD or the like. As shown in FIG. 41, contact holes 129 are formed in second interlayer insulating film 127 in portions located on upper electrodes 125 of capacitors 120. Then, an interconnection layer 131 of aluminum (Al) or the like is formed on inner surfaces of contact holes 129 and on second interlayer insulating film 127 by sputtering or the like. The DRAM shown in FIG. 30 is formed through the aforementioned steps.
In the aforementioned DRAM, it is possible to increase the capacitances of the capacitors having high dielectric films. However, the aforementioned conventional DRAM has a problem as hereafter described with reference to FIG. 42. FIG. 42 is a sectional view showing connected portions of each capacitor 120 and each plug 118 in the conventional DRAM.
Referring to FIG. 42, overetching is carried out so as to prevent the material of plug 118 from leaving on first interlayer insulating film 115, whereby the upper surface of plug 118 is lower in the contact hole 117, as hereinabove described. Thus, a step is defined between an upper surface 115a of first interlayer insulating film 115 and that of plug 118.
Barrier layer 119, lower electrode 121, high dielectric film 123 and upper electrode 125 are formed along the upper surface of plug 118 and the upper surface 115a of first interlayer insulating film 115. Barrier layer 119, lower electrode 121, high dielectric film 123 and upper electrode 125 are mainly formed by sputtering, as hereinabove described. In particular, high dielectric film 123 is formed by sputtering, since it is difficult to attain desired film characteristics by CVD.
In general, a layer which is formed by sputtering is inferior in step coverage. Therefore, locally thinned portions are defined in barrier layer 119, lower electrode 121, high dielectric film 123 and upper electrode 125 along the step.
For example, high dielectric film 123 has a thickness t in a portion located on the upper surface 115a of first interlayer insulating film 115, while its thickness is reduced to t1 in a portion located on the step. Such a locally thinned portion of high dielectric film 123 leads to the following problem:
The lower limit for the thickness of high dielectric film 123 inevitably depends on a leakage current and a withstand voltage. In other words, it is necessary to decide the thickness of high dielectric film 123 in capacitor 120 to be in excess of the lower limit in the smallest portion.
It is assumed here that the lower limit for the thickness of high dielectric film 123 is a .ANG. and the thickness t1 of the portion located on the step is about half the thickness t of the portion located on the upper surface 115a of first interlayer insulating film 115. In this case, the thickness t of the high dielectric film 123 must be in excess of (2.times.a) .ANG. in the portion located on the upper surface 115a of first interlayer insulating film 115.
On the other hand, the amount of stored charges is in proportion to the inverse number of the thickness of the dielectric film. Therefore, the amount of stored charges is increased, i.e., the capacitance is increased as the dielectric film is reduced in thickness. In the aforementioned case, however, the amount of stored charges is substantially halved since the thickness of high dielectric film 123 is substantially doubled in most part of the capacitor 120. Consequently, the capacitance of the capacitor 120 is disadvantageously reduced.